Page 1 of 6

www.siliconsupplies.com

Die Size (Unsawn)

2000 x 1450

79 x 57

µm

mils

Minimum Bond Pad Size

120 x 120

4.72 x 4.72

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

High Speed CMOS Logic – 54HC175

Quad D-Type Flip-Flop Logic IC with Reset in bare die form

Rev 1.0

21/11/17



Output Drive Capability: 10 LSTTL Loads



Outputs Directly Interface to CMOS, NMOS, and TTL



Low Input Current: 1µA



High Noise Immunity Characteristics of CMOS



Operating Voltage Range: 2.0 to 6.0 V



Direct drop-in replacement for obsolete components

in long term programs.

Features:

The following part suffixes apply:



No suffix - MIL-STD-883 /2010B Visual Inspection



“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT



“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification



Default – Die in Waffle Pack (100 per tray capacity)



Sawn Wafer on Tape – On request



Unsawn Wafer – On request



Die Thickness <> 350µm(14 Mils) – On request



Assembled into Ceramic Package – On request

The 54HC175 is fabricated using a 2.5µm 5V CMOS

process and consists of four D-Type flip–flops each

with separate D input and common Reset and Clock

inputs. The logic level present at the “D” input is

transferred to the Q output during the positive-going

transition of the clock pulse. Reset is clock

independent and is accomplished by a low level on the

Reset line. The device is useful for applications where

both the true and complement outputs are required

and the clock and master reset are common to all

storage elements.

Description

Ordering Information

Die Dimensions in µm (mils)

2000 (79)