Data Sheet S11421EJ2V0DS00

11

µµµµPD16644

Switching Characteristics (TA =

−−−−10 to +75°C, VDD1 = 3.0 to 3.6 V, VDD2 = 3.0 to 3.6 V or 4.5 to 5.5 V, VSS1 = VSS2

= 0 V, tr = tf = 3.0 ns)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

tPLH1

CL = 15 pF

7.0

12.0

ns

Start Pulse Delay Time

tPHL1

CL = 15 pF

7.0

12.0

ns

tPLH21

2.5

µs

tPLH31

VO: 0.1 V

→3.2 V

10

µs

tPHL21

2.5

µs

tPHL31

VDD2 = 3.3 V

2 k

Ω +75 pF × 2

VO: 3.2 V

→0.1 V

10

µs

tPLH22

2.5

µs

tPLH32

VO: 0.1 V

→4.9 V

10

µs

tPHL22

2.5

µs

Driver Output Delay Time

tPHL32

VDD2 = 5.0 V

2 k

Ω +75 pF × 2

VO: 4.9 V

→0.1 V

10

µs

CI1

STHR (STHL), TA = 25

°C15

20

pF

CI2

V0 to V10, TA = 25

°C

100

150

pF

Input Capacitance

CI3

STHR (STHL), other than V0 to V10

TA = 25

°C

10

15

pF

Timing Requirements (TA = –10 to +75

°C, VDD1 = 3.0 to 3.6 V, VSS1 = 0 V, tr = tf = 3.0 ns)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Clock Pulse Width

PWCLK

25

ns

Clock Low Period

PWCLK (L)

4ns

Clock High Period

PWCLK (H)

4ns

Strobe High Period

PWSTB(H)

2CLK

Strobe Low Period

PWSTB(L)

2CLK

Data Setup Time

tSETUP1

4ns

Data Hold Time

tHOLD1

0ns

Start Pulse Setup Time

tSETUP2

4ns

Start Pulse Hold Time

tHOLD2

0ns

Start Pulse Low Period

tSPL

2CLK

Start Pulse Rise Time

tSPR

64

CLK

Strobe Setup Time

tSETUP3

1CLK

Data Invalid Period

tINV

1CLK

Last Data Timing

tLDT

1CLK

CLK-STB Time

tCLK-STB

CLK

↑→STB↑ or ↓

7ns

STB-CLK Time

tSTB-CLK

STB

↑ or ↓→CLK↑

7ns