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UPD16732 Datasheet(PDF) 13 Page - Renesas Technology Corp |
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UPD16732 Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 18 page  Data Sheet S12933EJ2V0DS00 11 µµµµ PD16732 Measurement Condition Timing Requirement (TA = –10 to +75 °C, VDD1 = 3.3 V ±±±±0.3 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Clock Pulse Width PWCLK 25 ns Clock Pulse High Period PWCLK(H) 4ns Clock Pulse Low Period PWCLK(L) 4ns Data Setup Time tSETUP1 4ns Data Hold Time tHOLD1 0ns Start Pulse Setup Time tSETUP2 4ns Start Pulse Hold Time tHOLD2 0ns POL2 Setup Time tSETUP3 4ns POL2 Hold Time tHOLD3 0ns Start Pulse Low Period tSPL 6ns 2CLK STB Pulse Width PWSTB 4 µ s Data Invalid Period tINV 1CLK Last Data Timing tLDT 2CLK CLK-STB Time tCLK-STB CLK ↑ → STB ↑ 6ns STB-CLK Time tSTB-CLK STB ↑ → CLK ↑ 6ns Time Between STB and Start Pulse tSTB-STH STB ↑ → STHR(STHL) ↑ 2CLK POL-STB Time tPOL-STB POL ↑ or ↓ → STB ↑ –5 ns STB-POL Time tSTB-POL STB ↓ → POL ↓ or ↑ 6ns OUTPUT RL RL RL RL RL=1k CL CL CL CL CL CL=15pF RL 5 5 |
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