µPD16857

11

Data Sheet S13908EJ1V0DS00

The switching characteristics shown on the preceding pages are specified as follow (“output at one side” means

output B for H-bridge output A, or output A for output B).

[Rise time]

Rise time when the output at one side is fixed to the low level (specified on current ON).

[Fall time]

Fall time when the output at one side is fixed to the high level (specified on current ON).

[Rising delay time]

Rising delay time when the output at one side is fixed to the low level (specified on current ON).

[Falling delay time]

Falling delay time when the output at one side is fixed to the high level (specified on current ON).

[Change in rising delay time]

Change (difference) in the rising delay time between when the output at one side is fixed to the low level and when

the output at the other side is fixed to the high level.

[Change in falling delay time]

Change (difference) in the falling delay time between when the output at one side is fixed to the low level and when

the output at the other side is fixed to the high level.

[Rising delay time differential]

Difference in rising delay time between output A and output B.

[Falling delay time differential]

Difference in falling delay time between output A and output B.

Caution Because this LSI switches a high current at high speeds, surge may occur due to the VM and GND

wiring and inductance and degrade the performance of the LSI.

On the PWB, keep the pattern width of the VM and GND lines as wide and short as possible, and

insert the bypass capacitors between VM and GND at location as close to the LSI as possible.

Connect a low inductance magnetic capacitor (4700 pF or more) and an electrolytic capacitor of

10

µF or so, depending on the load current, in parallel.