L6730C datasheet(20/50 Pages) STMICROELECTRONICS

20 / 50 page

Device description

L6730C - L6730D

20/50

5.8

Monitoring and protections

The output voltage is monitored by the FB pin. If it is not within ±10% (typ.) of the programmed

value, the Power-Good (PGOOD) output is forced low. The PGOOD signal can be delayed by

adding an external capacitor on PGDelay pin (see Table 3: Pins connection and Figure 11.);

this can be useful to perform cascade sequencing. The delay can be calculated with the

following formula:

The device provides over-voltage-protection: when the voltage sensed on FB pin reaches a

value 20% (typ.) greater than the reference, the low-side driver is turned on. If the OVP not-

latched mode has been set the low-side MOSFET is kept on as long as the over voltage is

detected (see Figure 12.).If OVP latched-mode has been set the low-side MOSFET is turned

on until Vcc is toggled (see Figure 13.). In case of latched-mode OVP the OSC pin is forced

high (4.5V typ.) if an over voltage is detected. .

Figure 11. PGOOD signal

Figure 12. OVP not latched

()

PGDelay

⋅

= 5

[pF] (3)

LGate

OSC

L6730C Datasheet(PDF) 20 Page - STMicroelectronics