UPD17243 datasheet(39/104 Pages) RENESAS

39 / 104 page

Data Sheet U15002EJ1V1DS

µPD17240, 17241, 17242, 17243, 17244, 17245, 17246

3.8

INT Pin

The INT pin functions alternately as the P1B0 pin. To use the INT pin, set INTSEL (bit 1 of address 1FH) of the

This pin inputs an external interrupt request signal. The IRQ flag (RF: bit 0 of address 3EH) is set at either the

rising or falling edge of the signal input to this pin.

The status of this pin can be read by using the INT flag (RF: bit 0 of address 0FH). When a high level is input to

the pin, the INT flag is set to “1”; when a low level is input, the flag is reset to “0” (refer to 8.2.1 INT).

Table 3-1.

Relationship Between Port Register and Each Pin

Bank Address

Target Port

Bit

Output

Read Contents

Written Contents

After Reset

Format

Input mode Output mode Input mode Output mode

70H

Port 0A

P0A3

Input

Pin status

–

Input mode

P0A2

(with pull-up

P0A1

resistor)

P0A0

71H

Port 0B

P0B3

N-ch

Output latch Output latch Output latch

P0B2

open drain

P0B1

P0B0

72H

Port 0C

P0C3

Output mode

P0C2

(low-level

P0C1

output)

P0C0

73H

Port 0D

P0D3

P0D2

P0D1

P0D0

6FH

Port 0E

P0E3

CMOS

P0E2

push-pull

P0E1

or N-ch

P0E0

open drain

70H

Port 1A

P1A2

CMOS

P1A1

push-pull

P1A0

or N-ch

open drain

71H

Port 1B

P1B0

Input

–

Input mode

(when key

matrix not

used and no

resistor

connected)

Input mode

(when key

matrix not

used and no

pull-up resistor

connected)

Input mode

(when key

matrix not

used and no

resistor

connected)

UPD17243 Datasheet(PDF) 39 Page - Renesas Technology Corp

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