M41T82 datasheet(30/58 Pages) STMICROELECTRONICS

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Clock operation

M41T82 M41T83

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3.4.2

Analog calibration (programmable load capacitance)

A second method of calibration employs the use of programmable internal load capacitors

to adjust (or trim) the oscillator frequency.

By design, the oscillator is intended to be 0 ppm ± crystal accuracy at room temperature

(25°C, see Figure 17 on page 31). For a 12.5pF crystal, the default loading on each side of

the crystal will be 25pF. For incrementing or decrementing the calibration value,

capacitance will be added or removed in increments of 0.25pF to each side of the crystal.

Internally, CLOAD of the oscillator is changed via two digitally controlled capacitors, CXI and

CXO, connected from the XI and XO pins to ground (see Figure 16 on page 27). The

effective on-chip series load capacitance, CLOAD, ranges from 3.5pF to 17.4pF, with a

nominal value of 12.5pF (AC0-AC6 = ‘0’).

The effective series load capacitance (CLOAD) is the combination of CXI and CXO:

Seven analog calibration bits, AC0 to AC6, are provided in order to adjust the on-chip load

capacitance value for frequency compensation of the RTC. Each bit has a different weight

for capacitance adjustment. An Analog Calibration Sign (ACS) bit determines if capacitance

is added (ACS bit = ‘0’, negative calibration) or removed (ACS bit = ‘1’, positive calibration).

The majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency

by removing capacitance) due to the typical characteristic of quartz crystals to slow down

due to changes in temperature, but negative calibration is also available.

Since the Analog Calibration Register adjustment is essentially “pulling” the frequency of the

oscillator, the resulting frequency changes will not be linear with incremental capacitance

changes. The equations which govern this mechanism indicate that smaller capacitor

values of Analog Calibration adjustment will provide larger increments. Thus, the larger

values of Analog Calibration adjustment will produce smaller incremental frequency

changes. These values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the

highest capacitance settings. The range provided by the Analog Calibration Register

adjustment with a typical surface mount crystal is approximately ±30 ppm around the AC6-

AC0 = 0 default setting because of this property (see Table 7 on page 31).

LOAD

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