SST36VF1601C datasheet(2/34 Pages) SST

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Data Sheet

16 Mbit Dual-Bank Flash Memory

SST36VF1601C / SST36VF1602C

S71249-06-000

1/06

SuperFlash technology provides fixed Erase and Program

times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose

Erase and Program times increase with accumulated

Erase/Program cycles.

To meet high-density, surface-mount requirements, these

devices are offered in 48-ball TFBGA and 48-lead TSOP

packages. See Figures 5 and 6 for pin assignments.

Device Operation

Memory operation functions are initiated using standard

microprocessor write sequences. A command is written by

asserting WE# low while keeping CE# low. The address

bus is latched on the falling edge of WE# or CE#, which-

ever occurs last. The data bus is latched on the rising edge

of WE# or CE#, whichever occurs first.

Auto Low Power Mode

These devices also have the Auto Lower Power mode

which puts them in a near standby mode within 500 ns

after data has been accessed with a valid Read operation.

This reduces the IDD active Read current to 4 µA typically.

While CE# is low, the devices exit Auto Low Power mode

with any address transition or control signal transition used

to initiate another Read cycle, with no access time penalty.

Read Operation

The Read operation is controlled by CE# and OE#; both

have to be low for the system to obtain data from the out-

puts. CE# is used for device selection. When CE# is high,

the chip is deselected and only standby power is con-

sumed. OE# is the output control and is used to gate data

from the output pins. The data bus is in a high impedance

state when either CE# or OE# is high. Refer to the Read

cycle timing diagram for further details (Figure 7).

Program Operation

These devices are programmed on a word-by-word or

byte-by-byte basis depending on the state of the BYTE#

pin. Before programming, one must ensure that the sector

which is being programmed is fully erased.

The Program operation is accomplished in three steps:

1. Software Data Protection is initiated using the

three-byte load sequence.

2. Address and data are loaded.

During the Program operation, the addresses are

latched on the falling edge of either CE# or WE#,

whichever occurs last. The data is latched on the

rising edge of either CE# or WE#, whichever

occurs first.

3. The internal Program operation is initiated after

the rising edge of the fourth WE# or CE#, which-

ever occurs first. The Program operation, once ini-

tiated, will be completed typically within 7 µs.

See Figures 8 and 9 for WE# and CE# controlled Program

operation timing diagrams and Figure 23 for flowcharts.

During the Program operation, the only valid reads are

Data# Polling and Toggle Bit. During the internal Program

operation, the host is free to perform additional tasks. Any

commands issued during an internal Program operation

are ignored.

Sector- (Block-) Erase Operation

These devices offer both Sector-Erase and Block-Erase

operations. These operations allow the system to erase the

devices on a sector-by-sector (or block-by-block) basis. The

sector architecture is based on a uniform sector size of 2

KWord. The Block-Erase mode is based on a uniform block

size of 32 KWord. The Sector-Erase operation is initiated by

executing a six-byte command sequence with a Sector-

Erase command (30H) and sector address (SA) in the last

bus cycle. The Block-Erase operation is initiated by execut-

ing a six-byte command sequence with Block-Erase com-

mand (50H) and block address (BA) in the last bus cycle.

The sector or block address is latched on the falling edge of

the sixth WE# pulse, while the command (30H or 50H) is

latched on the rising edge of the sixth WE# pulse. The inter-

nal Erase operation begins after the sixth WE# pulse. Any

commands issued during the Sector- or Block-Erase opera-

tion are ignored except Erase-Suspend and Erase-

Resume. See Figures 13 and 14 for timing waveforms.

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