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ADL5308ACCZ-R7 Datasheet(PDF) 4 Page - Analog Devices |
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ADL5308ACCZ-R7 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 22 page ![]() Data Sheet ADL5308 SPECIFICATIONS analog.com Rev. 0 | 4 of 22 Table 1. Electrical Specifications (Continued) Parameter Test Conditions/Comments Min Typ Max Unit Input Capacitance 1 pF Glitch Rejection 50 ns SERIAL-INTERFACE TIMING SPECIFICATIONS Figure 2. I2C Timing Diagram Table 2. I2C Timing Specifications Parameter Description Min Typ Max Unit fSCL(MAX) = 1/t1 Maximum SCL clock frequency 400 kHz t3 Minimum SCL low period 0.65 1.3 μs t2 Minimum SCL high period 50 600 ns t9 Minimum bus free time between STOP/START condition 0.12 1.3 μs t4 Minimum hold time after (repeated) START condition 140 600 ns t7 Minimum repeated START condition setup-time 30 600 ns t8 Minimum STOP condition setup-time 30 600 ns t6 Minimum data-hold time input −100 0 ns t6 Minimum data-hold time output 300 600 900 ns t5 Minimum data setup-time input 30 100 ns tSP(MAX) Maximum suppressed spike pulse width 50 110 250 ns tRST Stuck bus reset time (condition: SCL or SDA held low) 25 66 ms CX SCL, SDA input capacitance 5 10 pF |
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