TAS5112ADFD datasheet(12/22 Pages) TI

12 / 22 page

TAS5112A

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

www.ti.com

In practice this means that the DVDD-to-PWM processor

(front-end) should be stable and initialization should be

completed before RESET is de-asserted to the back end.

CONTROL I/O

Shutdown Pin: SD

The SD pin functions as an output pin and is intended for

protection-mode signaling to, for example, a controller or

other front-end device. The pin is open-drain with an

internal pullup resistor to DVDD.

The logic output is, as shown in the following table, a

combination of the device state and RESET input:

RESET

DESCRIPTION

Reserved

Device in protection mode, i.e., UVP and/or OC

and/or OT error

1(2)

Device set high-impedance (Hi-Z), SD forced high

Normal operation

(2) SD is pulled high when RESET is asserted low independent

of chip state (i.e., protection mode). This is desirable to

maintain compatibility with some TI PWM front ends.

Temperature Warning Pin: OTW

The OTW pin gives a temperature warning signal when

temperature exceeds the set limit. The pin is of the

open-drain type with an internal pullup resistor to DVDD.

OTW

DESCRIPTION

Junction temperature higher than 125

°C

Junction temperature lower than 125

°C

Overall Reporting

The SD pin, together with the OTW pin, gives chip state

information as described in Table 1.

Table 1. Error Signal Decoding

OTW

DESCRIPTION

Overtemperature error (OTE)

Overtemperature warning (OTW)

Overcurrent (OC) or undervoltage (UVP) error

Normal operation, no errors/warnings

Chip Protection

The TAS5112A protection function is implemented in a

closed loop with, for example, a system controller and TI

PWM processor. The TAS5112A contains three individual

systems protecting the device against error conditions. All

of the error events covered result in the output stage being

set in a high-impedance state (Hi-Z) for maximum

protection of the device and connected equipment.

The device can be recovered by toggling RESET low and

then high, after all errors are cleared.

Overcurrent (OC) Protection

The device has individual forward current protection on

both high-side and low-side power stage FETs. The OC

protection works only with the demodulation filter present

at the output. See Demodulation Filter Design in the

Application Information section of the data sheet for design

constraints.

Overtemperature (OT) Protection

A dual temperature protection system asserts a warning

signal when the device junction temperature exceeds

125

°C. The OT protection circuit is shared by all

half-bridges.

Undervoltage (UV) Protection

Undervoltage lockout occurs when GVDD is insufficient

for proper device operation. The UV protection system

protects the device under power-up and power-down

situations. The UV protection circuits are shared by all

half-bridges.

Reset Function

The reset has two functions:

D Reset is used for re-enabling operation after a

latching error event.

D Reset is used for disabling output stage

switching (mute function).

The error latch is cleared on the falling edge of reset and

normal operation is resumed when reset goes high.

PROTECTION MODE

Autorecovery (AR) After Errors (PMODE0)

In autorecovery mode (PMODE0) the TAS5112A is

self-supported in handling of error situations. All protection

systems are active, setting the output stage in the

high-impedance state to protect the output stage and

connected equipment. However, after a short time period

the device autorecovers, i.e., operation is automatically

resumed provided that the system is fully operational.

The autorecovery timing is set by counting PWM input

cycles, i.e., the timing is relative to the switching frequency.

The AR system is common to both half-bridges.

TAS5112ADFD Datasheet(PDF) 12 Page - Texas Instruments

TAS5112ADFD Datasheet(HTML) 12 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL