AM69A datasheet(9/300 Pages) TI1

9 / 300 page

(3)

AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the

Nomenclature Description table

(4)

DDRSS2 and DDRSS3 are not available on the 27mm package variant of this SoC. DDR2/DDR3 should be not be used if software

compatibility is desired with systems that use the 27mm package

(5)

DDRSS0, DDRSS1, DDRSS2 and DDRSS3 must always be used in incremental order. For instance, when using a single LPDDR

component, it must be connected to DDR0_* interface. When using two LPDDR components, they must be connected to DDR0_* and

DDR1_* interfaces, and so forth.

(6)

DP, SGMII, USB3.0, and PCIE share total of 16 SerDes lanes.

(7)

AM69 CPSW supports up to 8 ports using the following instances and signals and modes of operation:

•

PORT1 Signals: SGMII1, Modes: One of 5Gb, 10Gb USXGMII/XFI, 2.5 Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII

•

PORT2 Signals: SGMII2, Modes: One of 5Gb, 10Gb USXGMII/XFI, 2.5 Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII

•

PORTn (n=3 thru 8) Signals: SGMIIn, Modes: One of 2.5 Gb SGMII/XAUI, 1Gb SGMII, 5Gb QSGMII

If QSGMII is used on any SGMII Port 1 thru 4, then SGMII1/2/3/4 cannot be used for Ethernet functionality since all 4 internal CPSW

ports map to the selected QSGMII SERDES port.

If QSGMII is used on any SGMII Port 5 thru 8, then SGMII5/6/7/8 cannot be used for Ethernet functionality since all 4 internal CPSW

ports map to the selected QSGMII SERDES port.

(8)

Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1.

(9)

J784S4 is the base part number for the superset device. Software should constrain the features used to match the intended production

device.

(10) OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts.

(11) Hyperlink is not supported on this SoC. System designs should not use the signals HYP_*, HYP0_*, HYP1_*.

(12) MCU_R5FSS0 includes Dual-Core R5F that provides Device Management functionality, and is reserved for executing TI provided

code.

R5FSS1 is a Dual-Core R5F that provides Multimedia Control functionality, and is reserved for executing TI provided code.

(13) The Deep Learning Accelerator C7x + MMA are reserved for executing TI provided code, and are not available for custom code.

www.ti.com

AM69A, AM69

SPRSP92A – FEBRUARY 2023 – REVISED AUGUST 2023

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AM69A Datasheet(PDF) 9 Page - Texas Instruments