STD55NH2LL - STD55NH2LL-1

Appendix A

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Appendix A

The power losses associated with the FETs in a synchronous buck converter can be

estimated using the equations shown in the table below. The formulas give a good

approximation, for the sake of performance comparison, of how different pairs of devices

affect the converter efficiency. However a very important parameter, the working

temperature, is not considered. The real device behavior is really dependent on how the

heat generated inside the devices is removed to allow for a safer working junction

temperature.

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The low side (SW2) device requires:

●

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Small Qgls to reduce the gate charge losses

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Small Coss to reduce losses due to output capacitance

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Small Qrr to reduce losses on SW1 during its turn-on

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The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source

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voltage to avoid the cross conduction phenomenon;

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The high side (SW1) device requires:

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Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on

the gate

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Small Qg to have a faster commutation and to reduce gate charge losses

●

Figure 19.

Buck converter: power losses estimation