CS5172GD8 datasheet(12/21 Pages) ONSEMI

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The first zero generated by C1 and R1 is:

fZ1 +

pC1R1

The phase lead provided by this zero ensures that the loop

has at least a 45

° phase margin at the crossover frequency.

Therefore, this zero should be placed close to the pole

generated in the power stage which can be identified at

frequency:

fP +

pCORLOAD

where:

CO = equivalent output capacitance of the error amplifier

≈120pF;

RLOAD= load resistance.

The high frequency pole, fP2, can be placed at the output

filter’s ESR zero or at half the switching frequency. Placing

the pole at this frequency will cut down on switching noise.

The frequency of this pole is determined by the value of C2

and R1:

fP2 +

pC2R1

One simple method to ensure adequate phase margin is to

design the frequency response with a −20 dB per decade

slope, until unity−gain crossover. The crossover frequency

should be selected at the midpoint between fZ1 and fP2 where

the phase margin is maximized.

Figure 32. Bode Plot of the Compensation Network

Shown in Figure 31

Frequency (LOG)

fP1

fZ1

fP2

Negative Voltage Feedback

Since the negative error amplifier has finite input

impedance as shown in Figure 33, its induced error has to be

considered. If a voltage divider is used to scale down the

negative output voltage for the NFB pin, the equation for

calculating output voltage is:

*VOUT +

*2.5 (R1 ) R2)

*10 mA

−

Figure 33. Negative Error Amplifier and NFB Pin

2 V

200 k

Negative Error−Amp

NFB

RIN

−VOUT

250 k

It is shown that if R1 is less than 10 k, the deviation from

the design target will be less than 0.1 V. If the tolerances of

the negative voltage reference and NFB pin input current are

considered, the possible offset of the output VOFFSET varies

in the range of:

*0.0.5 (R1 ) R2)

* (15 mA

R1)

v VOFFSET

0.0.5 (R1

) R2)

* (5 mA

R1)

VSW Voltage Limit

In the boost topology, VSW pin maximum voltage is set by

the maximum output voltage plus the output diode forward

voltage. The diode forward voltage is typically 0.5 V for

Schottky diodes and 0.8 V for ultrafast recovery diodes

VSW(MAX) + VOUT(MAX))VF

where:

VF = output diode forward voltage.

In the flyback topology, peak VSW voltage is governed by:

VSW(MAX) + VCC(MAX))(VOUT)VF)

where:

N = transformer turns ratio, primary over secondary.

When the power switch turns off, there exists a voltage

spike superimposed on top of the steady−state voltage.

Usually this voltage spike is caused by transformer leakage

inductance charging stray capacitance between the VSW and

PGND pins. To prevent the voltage at the VSW pin from

exceeding the maximum rating, a transient voltage

suppressor in series with a diode is paralleled with the

primary windings. Another method of clamping switch

voltage is to connect a transient voltage suppressor between

the VSW pin and ground.

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