MP8020 – IEEE 802.3af/at/bt, PoE, POWERED DEVICE INTERFACE

MP8020 Rev. 1.0

MonolithicPower.com

18

2/17/2022

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the device enters current foldback mode

(reaches the inrush current limit), VSRC

drops. At the same time, PG is pulled low.

 If the internal MOSFET or external

MOSFET triggers the fast-off current limit,

the MP8020 quickly turns off the related

MOSFET and then restarts with a delay.

Power Good (PG) and Delay

The MP8020 has one PG output to enable the

downstream DC/DC converter after the inrush

period finishes and the PSE is ready to provide

high power. PG is an open-drain output with a

voltage rating up to 100V.

PG goes to a high-impedance (Hi-Z) state when

the device meets all of the following conditions:

 The device has changed to the steady

current limit, which means that the inrush

period is complete.

 The 90ms delay (tDELAY) from UVLO has

completed.

 A wall power adapter is detected on AUX,

and VADP exceeds the UVLO threshold (see

Figure 3).

PSE Power On

VDD > UVLO_R?

Inrush Current

Current < 75% of

Inrush Limit?

Change to Steady

State Current Limit

90ms Timer

Timer ran out?

Yes

Yes

Yes

No

No

PG rises to high

BT, TYP1, and TYP2 operate

based on PSE type

Both are ok

Yes

PG and GATE1 drops

VDD - VSS < UVLO_F?

Yes

PG, BT, TYP1, and

TYP2 signals reset

No

PSE Power Off

Drive GATE1

VDD - VSRC > 10V

for 1ms?

VDD - VSRC < 10V

Yes

Figure 3: PG Logic

The PG signal resets when the VDD UVLO turn-

off

threshold

(VDD_F)

is

triggered,

over-

temperature protection (OTP) occurs, or if VDD -

VSRC > 10V for more than 1ms. The 90ms timer

only works after VDD UVLO is triggered.

PSE and Allocated Power Indicators

IEEE802.3bt supports 4 different PSE power

supplies. The BT, TYP1, and TYP2 pins

indicate the PSE-allocated power type. Table 3

on page 19 shows the detailed power level

indicators. Note that the indicator only displays

high when it is in logic high and pulled up to a

high voltage via an external pull-up resistor.

The TYP1, TYP2, and BT signals are active

after a tDELAY of 90ms (same as the PG signal).

The outputs become inactive (high-impedance)

when VDD falls below its UVLO threshold, or if

OTP is triggered. The BT, TYP1, and TYP2

signals are latched in the MP8020 after start-up

and do not reset until VDD drops to the mark

event reset threshold.

If an adapter is detected, the TYP1 and TYP2

pins go low and BT goes high.

Table 4 on page 19 shows some power

demotion cases.