PSD835G2 datasheet(22/102 Pages) STMICROELECTRONICS

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PSD835G2

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Table 19. Flash Boot Protection Register

Note: Bit Definitions:

Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.

Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected.

Security_Bit 0 = Security Bit in device has not been set.

Security_Bit 1 = Security Bit in device has been set.

Table 20. JTAG Enable Register

Note: Bit Definitions:

JTAG_Enable 1 = JTAG Port is enabled.

JTAG_Enable 0 = JTAG Port is disabled.

Table 21. Page Register

Note: Bit Definitions:

Configure Page input to PLD. Default is PGR7-PGR0=00.

Table 22. PMMR0 Register

Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers.

2. Bit Definitions:

APD Enable0 = Automatic Power-down (APD) is disabled.

1 = Automatic Power-down (APD) is enabled.

PLD Turbo0 = PLD Turbo is on.

1 = PLD Turbo is off, saving power.

PLD Array CLK0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo Bit is off.

1 = CLKIN to the PLD AND array is disconnected, saving power.

PLD MCells CLK0 = CLKIN to the PLD Macrocells is connected.

1 = CLKIN to the PLD Macrocells is disconnected, saving power.

Table 23. PMMR2 Register

Note: Bit Definitions:

PLD Array Addr

0 = Address A7-A0 are connected to the PLD array.

1 = Address A7-A0 are blocked from the PLD array, saving power.

(Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4)

PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected.

1 = CNTL2 input to the PLD AND array is disconnected, saving power.

PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected.

1 = CNTL1 input to the PLD AND array is disconnected, saving power.

PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected.

1 = CNTL0 input to the PLD AND array is disconnected, saving power.

PLD Array ALE

0 = ALE input to the PLD AND array is connected.

1 = ALE input to the PLD AND array is disconnected, saving power.

PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.

1 = WRH/DBE input to the PLD AND array is disconnected, saving power.

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1

Bit 0

Security_Bit

not used

Sec3_Prot

Sec2_Prot

Sec1_Prot

Sec0_Prot

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1

Bit 0

not used

JTAGEnable

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1

Bit 0

PGR 7PGR 6PGR 5PGR 4PGR 3PGR 2PGR 1PGR 0

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1

Bit 0

not used

(set to ’0’)

not used

(set to ’0’)

PLD

MCells CLK

PLD

Array CLK

PLD

Turbo

not used

(set to ’0’)

APD

Enable

not used

(set to ’0’)

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1

Bit 0

not used

(set to ’0’)

PLD

Array WRH

PLD

Array ALE

PLD Array

CNTL2

PLD Array

CNTL1

PLD Array

CNTL0

not used

(set to ’0’)

PLD Array

Addr

PSD835G2 Datasheet(PDF) 22 Page - STMicroelectronics

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