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PACKAGE DISSIPATION RATINGS

ABSOLUTE MAXIMUM RATINGS

SN65MLVD047

SLLS606A – MARCH 2004 – REVISED JULY 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PART NUMBER

PACKAGE MARKING

PACKAGE/CARRIER

SN65MLVD047D

MLVD047

16-Pin SOIC/Tube

SN65MLVD047DR

MLVD047

16-Pin SOIC/Tape and Reel

SN65MLVD047PW

MLVD047

16-Pin TSSOP/Tube

SN65MLVD047PWR

MLVD047

16-Pin TSSOP/Tape and Reel

PCB JEDEC

DERATING FACTOR

PACKAGE

STANDARD

POWER RATING

POWER RATING

D(16)

898 mW

7.81 mW/

°C

429 mW

592 mW

5.15 mW/

°C

283 mw

PW(16)

945 mW

8.22 mW/

°C

452 mw

(1)

This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.

(2)

In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.

(3)

In accordance with the High-K thermal metric definitions of EIA/JESD51-7.

UNITS

–0.5 V to 4 V

Input voltage range

A, EN, EN

–0.5 V to 4 V

Output voltage range

Y, Z

–1.8 V to 4 V

Y and Z

±9 kV

All pins

±4 kV

Electrostatic discharge

All pins

±1500 V

All pins

200 V

Junction temperature

140

°C

Continuous power dissipation

See Dissipation Rating Table

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values, except differential I/O bus voltages, are with respect to the circuit ground terminal.

(3)

Tested in accordance with JEDEC Standard 22, Test Method A114-B.

(4)

Tested in accordance with JEDEC Standard 22, Test Method C101-A.

(5)

Tested in accordance with JEDEC Standard 22, Test Method A115-A.

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