May 4, 2020

CONFIDENTIAL INFORMATION Rev. 1.2

SABRE9006A Datasheet

11

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-

8800 • Fax (408) 643-8801

System Clock (XI / MCLK)

A system clock is required for proper operation of the digital filters and modulation circuitry.

The system clock must be greater than 192 x fs for SERIAL/DSD inputs, or greater than 386 x fs for SPDIF input.

Data Type

Valid MCLK Frequencies

DSD Data

50MHz > MCLK > 192 x fs , fs = 2.8224MHz/64

Serial Mode

50MHz > MCLK > 192 x fs

SPDIF Data

50MHz > MCLK > 386 x fs

Data Clock

This must be 64 x fs for SERIAL / DSD modes, and is not required for SPDIF mode.

Digital Filters

There are numerous applications for a stereo DAC so for added flexibility; two digital filter settings are possible, sharp roll-off

and a slow roll-off for PCM mode. For DSD mode, there is 1 available filter with cutoff at 50kHz.

Serial Control Interface

The registers inside the chip are programmed via an I2C interface. The diagram below shows the timing for this interface.

The chip address c

an be set to 2 different settings via the “ADDR” pin. The table below summarizes this.

ADDR

CHIP ADDRESS

0

0x90

1

0x92

Table 7

Diagram 1

Notes:

1.

The “ADDR” pin is used to create the CHIP ADDRESS. (0x90, 0x92)

2.

The first byte

after the chip address is the “ADDRESS” this is the register address.

3.

The second byte after the CHIP ADDRESS

is the “DATA” this is the data to be programmed into the register at the

previous “ADDRESS”.

4.

Compatible with I2C-bus specification version 2.1 Standard-mode/Fast-mode.