TC1270AMAVRCTR datasheet(21/42 Pages) MICROCHIP

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DS20002035F-page 21

TC1270A/70AN/71A

4.5

Reset Generator Circuit

The output signals from the voltage detect circuit and

the manual Reset with glitch filter circuit are OR’d

together and used to activate the Reset generator

module.

After the Reset conditions have been removed (the MR

pin is no longer forced low and the input voltage is

greater than the trip point voltage), the Reset generator

circuit determines the Reset delay time-out required.

There are three options for the delay circuit. These are:

• 2.19 ms (typical) delay

• 35 ms (typical) delay

• 280 ms (typical) delay

4.5.1

RESET DELAY TIMER

The Reset Delay Timer ensures that the TC127XA

device will “hold” the embedded system in Reset until

the system voltage has stabilized. The Reset Delay

Timer time-out is shown in Table 4-4.

The Reset Delay Timer starts when the voltage detect

circuit output AND the manual Reset with glitch filter

circuit output become inactive. While the Reset Delay

Timer is active, the RST or RST pin is driven to the

active state. When the Reset Delay Timer times out,

the RST or RST pin is driven inactive.

The Reset Delay Timer (tRST) starts after the device

voltage rises above the “actual” trip point (VTRIP).

When the Reset Delay Timer times out, the Reset out-

put pin (RST/RST) is driven inactive.

The Reset Delay Timer is cleared if either, or both, the

voltage detector circuit output and the manual Reset

with glitch filter circuit output become active. The RST

or RST pin continues to be driven to the active state.

Figure 4-12 illustrates when the Reset Delay Timer

(tRST) is active or inactive.

4.5.2

EFFECT OF TEMPERATURE ON

RESET POWER-UP TIMER (tRPU)

The Reset Delay Timer time-out period (tRST)

determines how long the device remains in the Reset

condition. This time out is affected by the device VDD

and the temperature. Typical responses for varying

VDD values and temperatures are presented in

Figures 2-28, 2-29 and 2-30.

TABLE 4-4:

RESET DELAY TIMER

TIME OUTS

FIGURE 4-12:

Reset Power-Up Timer

Waveform.

tRST

Units

Min.

Typ.

Max.

1.09

2.19

4.38

17.5

140

280

560



This is the

minimum time that

the Reset Delay

Timer will “hold”

the Reset pin

active after VDD

rises above VTRIP

This is the

maximum time that

the Reset Delay

Timer will “hold”

the Reset pin

active after VDD

rises above VTRIP

Note 1: Shaded rows are custom-ordered time

outs.

VTRIP

VDD

RST

tRST

Reset Delay

Timer Inactive

Reset

Delay

Timer

Inactive

See Figures 2-9,

2-7 and 2-8

See Figures 2-12, 2-11 and 2-10

See Figures 2-9,

2-7 and 2-8

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