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WL102BC/PR/FP1R Datasheet(PDF) 2 Page - Zarlink Semiconductor Inc |
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WL102BC/PR/FP1R Datasheet(HTML) 2 Page - Zarlink Semiconductor Inc |
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2 / 10 page ![]() Features • Complete CMOS, single chip, radio transceiver controller • Hardware implemented Communication Control Block (CCB) • Protocol independent design using external flash memory • Internal 8051 and external processor options • Internal/external buffer and processor RAM • Block power down facility • PCMCIA/8bit processor host interface to buffer RAM • Up to 1Mbps/2 level or 2 Mbps/4 level operation The WL102B is a highly integrated CMOS wireless data controller designed to dramatically reduce the cost of radio data applications. It works with the WL600C RF IF chip and WL800 synthesiser chip to offer a complete solution for a frequency hopping, spread spectrum radio in the 2.4 to 2.45GHz ISM band. Its flexible design means that it can also be used in a wide range of other applications using a range of "proc- essor", protocols and additional memory options as well as radios at other frequencies. Related Documents WL600 (DS4581), WL800 (DS5241) and WL102B (DS4837) Datasheets Figure 1 - WL102 Minimum configuration block diagram WL102B Wireless Data Controller Advance Information DS4582 ISSUE 4.0 May 2000 Ordering Information WL102B/IG/TP1N 100 pin package WL102BC/PR/FP1R 144 pin package Communications Control Block Receive Transmit Status Control Address Data Control Port Pins Interrupt Buffer RAM 6K4 8051 System RAM 4K Counters Power Down Control Attribute Memory Configuration Control Data Address Memory Control Block Interrupt DMA WL102 |
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