WM8746SEDSSLASHR datasheet(8/32 Pages) WOLFSON

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WM8746

Production Data

March 2006, PD Rev 4.0

MASTER CLOCK TIMING

SCKI

SCKIL

SCKIH

SCKIY

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25

oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

System Clock Timing Information

SCKI System clock pulse width high

tSCKIH

SCKI System clock pulse width low

tSCKIL

SCKI System clock cycle time

tSCKIY

SCKI Duty cycle

40:60

60:40

Table 1 Master Clock Timing Requirements

DIGITAL AUDIO INTERFACE TIMING

BCLK

DACLRC

BCH

BCL

BCY

DIN0/1/2

LRSU

LRH

Figure 2 PCM Digital Audio Data Timing

Test Conditions

AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25

oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCKIN cycle time

tBCY

BCKIN pulse width high

tBCH

BCKIN pulse width low

tBCL

LRCIN set-up time to

BCKIN rising edge

tLB

LRCIN hold time from

BCKIN rising edge

tBL

DIN0/1/2 set-up time to

BCKIN rising edge

tDS

DIN0/1/2 hold time from

BCKIN rising edge

tDH

Table 2 PCM Digital Audio Timing

WM8746SEDS/R Datasheet(PDF) 8 Page - Wolfson Microelectronics plc

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