WM8778SEDSSLASHR datasheet(23/50 Pages) WOLFSON

23 / 50 page

Production Data

WM8778

PD Rev 4.0 April 2005

The transfer of data is complete when there is a low to high transition on DI while CL is high. After

receiving a complete address and data sequence the WM8778 returns to the idle state and waits for

another start condition. If a start or stop condition is detected out of sequence at any point during

data transfer (i.e. DI changes while CL is high), the device jumps to the idle condition.

Figure 21 2-wire Serial Interface

B[15:9] are Control Address Bits

B[8:0] are Control Data Bits

The WM8778 has two possible device addresses, which can be selected using the CE pin.

CE STATE

DEVICE ADDRESS

Low

0011010 (0 x 34h)

High

0011011 (0 x 36h)

Table 11 2-Wire MPU Interface Address Selection

HARDWARE MODE

Hardware mode is selected by applying a midrail voltage to the MODE pin, or by leaving it floating.

The circuit detects this condition and enables hardware mode. This allows limited control of the

internal functions using the three inputs CE, CL and DI. The table below gives a summary of the use

of each pin in hardware mode.

PIN NAME

FUNCTION

DESCRIPTION

CE\I2S

Interface Mode select

0 : Right Justified

1 : I

CL\IWL

Interface Wordlength select

0 : 20 bit (RJ), 16 bit (I

2S)

1 : 24 bit

DI\DEEMPH

De-emphasis on/off

0 : De-emphasis disabled

1 : De-emphasis enabled

Table 12 Hardware Mode Functions

WM8778SEDS/R Datasheet(PDF) 23 Page - Wolfson Microelectronics plc