WM8986GECOSLASHRV datasheet(21/87 Pages) WOLFSON

21 / 87 page

Pre-Production

WM8986

PP, Rev 3.1, February 2007

Figure 10 DAC Power Up and Down Sequence (not to scale)

SYMBOL

MIN

TYPICAL

MAX

UNIT

tline_midrail_on

300

tline_midrail_off

thp_midrail_on

300

thp__midrail_off

tdacint

2/fs

/fs

DAC Group Delay

51/fs

/fs

Table 3 Typical POR Operation (Typical Simulated Values)

Notes:

The lineout charge time, tline_midrail_on, is determined by the VMID pin charge time. This time is

dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and

AVDD1 power supply rise time. The values above were measured using a 4.7µF capacitor.

It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data

value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue

outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute

function has been applied to the signal beforehand.

The lineout discharge time, tline_midrail_off, is determined by the VMID pin discharge time. This

time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance.

The values above were measured using a 4.7µF capacitor.

The headphone charge time, thp_midrail_on, is dependent upon the value of VMID decoupling

capacitor and VMID pin input resistance and AVDD1 power supply rise time. The values above

were measured using a 4.7µF VMID decoupling capacitor.

The headphone discharge time, thp_midrail_off, is dependent upon the value of VMID decoupling

capacitor and VMID pin input resistance. The values above were measured using a 4.7µF

VMID decoupling capacitor.

The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for

normal DAC operation.

WM8986GECO/RV Datasheet(PDF) 21 Page - Wolfson Microelectronics plc