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AMC130M02DFMR Datasheet(PDF) 53 Page - Texas Instruments |
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AMC130M02DFMR Datasheet(HTML) 53 Page - Texas Instruments |
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53 / 88 page  8.6.3 MODE Register (Address = 02h) [Reset = 0510h] Return to the Summary Table. Figure 8-33. MODE Register 15 14 13 12 11 10 9 8 RESERVED REG_CRC_EN RX_CRC_EN CRC_TYPE RESET WLENGTH[1:0] R/W-00b R/W-0b R/W-0b R/W-0b R/W-1b R/W-01b 7 6 5 4 3 2 1 0 RESERVED TIMEOUT DRDY_SEL[1:0] DRDY_HiZ DRDY_FMT R/W-000b R/W-1b R/W-00b R/W-0b R/W-0b Table 8-17. MODE Register Field Descriptions Bit Field Type Reset Description 15:14 RESERVED R/W 00b Reserved Always write 00b 13 REG_CRC_EN R/W 0b Register map CRC enable 0b = Disabled 1b = Enabled 12 RX_CRC_EN R/W 0b SPI input CRC enable 0b = Disabled 1b = Enabled 11 CRC_TYPE R/W 0b SPI input and output, register map CRC type 0b = 16-bit CCITT 1b = 16-bit ANSI 10 RESET R/W 1b Reset Write 0b to clear the RESET bit in the STATUS register 0b = No reset 1b = Reset occurred 9:8 WLENGTH[1:0] R/W 01b Data word length selection 00b = 16 bits 01b = 24 bits 10b = 32 bits; LSB zero padding 11b = 32 bits; MSB sign extension 7:5 RESERVED R/W 000b Reserved Always write 000b 4 TIMEOUT R/W 1b SPI timeout enable 0b = Disabled 1b = Enabled 3:2 DRDY_SEL[1:0] R/W 00b DRDY pin signal source selection 00b = Most lagging enabled channel 01b = Logic OR of all the enabled channels 10b = Most leading enabled channel 11b = Most leading enabled channel 1 DRDY_HiZ R/W 0b DRDY pin state when conversion data are not available 0b = Logic high 1b = High impedance 0 DRDY_FMT R/W 0b DRDY signal format when conversion data are available 0b = Logic low 1b = Low pulse with a fixed duration www.ti.com AMC130M02 SBASAN9 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: AMC130M02 |
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