AD603ACHIPS datasheet(12/20 Pages) AD

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AD603

Rev. G | Page 12 of 20

SCALING

REFERENCE

GAIN-

CONTROL

INTERFACE

AD603

PRECISION PASSIVE

INPUT ATTENUATOR

FIXED-GAIN

AMPLIFIER

1NOMINAL VALUES.

R-2R LADDER NETWORK

VPOS

VNEG

GPOS

GNEG

VINP

COMM

0dB

–6.02dB

–12.04dB –18.06dB –24.08dB

–30.1dB

–36.12dB –42.14dB

RRR

Ω1

694

Ω1

6.44k

Ω1

VOUT

FDBK

Figure 29. Simplified Block Diagram

THE GAIN CONTROL INTERFACE

The attenuation is controlled through a differential, high

impedance (50 MΩ) input, with a scaling factor which is laser-

trimmed to 40 dB per volt, that is, 25 mV/dB. An internal band

gap reference ensures stability of the scaling with respect to

supply and temperature variations.

When the differential input voltage VG = 0 V, the attenuator

slider is centered, providing an attenuation of 21.07 dB. For the

maximum bandwidth range, this results in an overall gain of

10 dB (= −21.07 dB + 31.07 dB). When the control input is

−500 mV, the gain is lowered by 20 dB (= 0.500 V × 40 dB/V) to

−10 dB; when set to +500 mV, the gain is increased by 20 dB to

30 dB. When this interface is overdriven in either direction, the

gain approaches either −11.07 dB (= − 42.14 dB + 31.07 dB) or

31.07 dB (= 0 + 31.07 dB), respectively. The only constraint on

the gain control voltage is that it be kept within the common-

mode range (−1.2 V to +2.0 V assuming +5 V supplies) of the

gain control interface.

The basic gain of the AD603 can thus be calculated using the

following simple expression:

Gain (dB) = 40 VG +10

(1)

where VG is in volts. When Pin 5 and Pin 7 are strapped (see

next section), the gain becomes

Gain (dB) = 40 VG + 20 for 0 to +40 dB

and

Gain (dB) = 40 VG + 30 for +10 to +50 dB

(2)

The high impedance gain control input ensures minimal

loading when driving many amplifiers in multiple channel or

cascaded applications. The differential capability provides

flexibility in choosing the appropriate signal levels and

polarities for various control schemes.

For example, if the gain is to be controlled by a DAC providing

a positive only ground-referenced output, the Gain Control Low

(GNEG) pin should be biased to a fixed offset of 500 mV to set

the gain to −10 dB when Gain Control High (GPOS) is at zero,

and to 30 dB when at 1.00 V.

It is a simple matter to include a voltage divider to achieve other

scaling factors. When using an 8-bit DAC having an FS output

of 2.55 V (10 mV/bit), a divider ratio of 2 (generating 5 mV/bit)

would result in a gain-setting resolution of 0.2 dB/bit. The use

of such offsets is valuable when two AD603s are cascaded, when

various options exist for optimizing the S/N profile, as will be

shown later.

PROGRAMMING THE FIXED-GAIN AMPLIFIER

USING PIN STRAPPING

Access to the feedback network is provided at Pin 5 (FDBK).

The user may program the gain of the AD603’s output amplifier

using this pin, as shown in Figure 30, Figure 31, and Figure 32.

There are three modes: in the default mode, FDBK is

unconnected, providing the range +9 dB/+51 dB; when VOUT

and FDBK are shorted, the gain is lowered to −11 dB/+31 dB;

and when an external resistor is placed between VOUT and FDBK

any intermediate gain can be achieved, for example, −1 dB/+41

dB. Figure 33 shows the nominal maximum gain vs. external

resistor for this mode.

GPOS

GNEG

VINP

COMM

VPOS

VOUT

VNEG

FDBK

AD603

VC1

VC2

VIN

VPOS

VOUT

VNEG

Figure 30. −10 dB to +30 dB; 90 MHz Bandwidth

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