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AD8313

Rev. D | Page 13 of 24

INTERFACES

This section describes the signal and control interfaces and

their behavior. On-chip resistances and capacitances exhibit

variations of up to ±20%. These resistances are sometimes

temperature-dependent, and the capacitances may be voltage-

dependent.

POWER-DOWN INTERFACE, PWDN

The power-down threshold is accurately centered at the

midpoint of the supply as shown in Figure 24. If Pin 5 is left

unconnected or tied to the supply voltage (recommended), the

bias enable current is shut off, and the current drawn from the

supply is predominately through a nominal 300 kΩ chain

(20 µA at 3 V). When grounded, the bias system is turned on.

The threshold level is accurately at VPOS/2. When operating in

the device ON state, the input bias current at the PWDN pin is

approximately 5 µA for VPOS = 3 V.

PWDN

VPOS

75k

Ω

COMM

150k

Ω

50k

Ω

150k

Ω

TO BIAS

ENABLE

Figure 24. Power-Down Threshold Circuitry

SIGNAL INPUTS, INHI, INLO

The simplest low frequency ac model for this interface consists

of just a 900 Ω resistance, RIN, in shunt with a 1.1 pF input cap-

acitance, CIN, connected across INHI and INLO. Figure 25 shows

these distributed in the context of a more complete schematic.

The input bias voltage shown is for the enabled chip; when

disabled, it rises by a few hundred millivolts. If the input is

coupled via capacitors, this change may cause a low level signal

transient to be introduced, having a time constant formed by

these capacitors and RIN. For this reason, large coupling capacitors

should be well matched. This is not necessary when using the

small capacitors found in many impedance transforming

networks used at high frequencies.

1.25k

Ω

COMM

VPOS

INHI

INLO

VPOS

0.5pF

0.7pF

2.5k

Ω

2.5k

Ω

~0.75V

(1ST DETECTOR)

250

Ω

~1.4mA

125

Ω

125

Ω

1.25k

Ω

1.24V

GAIN BIAS

TO 2ND

STAGE

TO STAGES

1 TO 4

Figure 25. Input Interface Simplified Schematic

For high frequency use, Figure 26 shows the input impedance

plotted on a Smith chart. This measured result of a typical

device includes a 191 mil 50 Ω trace and a 680 pF capacitor to

ground from the INLO pin.

1.1pF

900

Ω

1.9GHz

Frequency

100MHz

900MHz

1.9GHz

2.5GHz

650

+jX

–j 400

–j 135

–j 65

–j 43

2.5GHz

900MHz

100MHz

AD8313 MEASURED

Figure 26. Typical Input Impedance

LOGARITHMIC/ERROR OUTPUT, VOUT

The rail-to-rail output interface is shown in Figure 27. VOUT can

run from within about 50 mV of ground, to within about 100 mV

of the supply voltage, and is short-circuit safe to either supply.

However, the sourcing load current, ISOURCE, is limited to that

which is provided by the PNP transistor, typically 400 µA.

Larger load currents can be provided by adding an external NPN

transistor (see the Applications section). The dc open-loop gain

of this amplifier is high, and it may be regarded as an integrator

having a capacitance of 2 pF (CINT) driven by the current-mode

signal generated by the summed outputs of the nine detector

stages, which is scaled approximately 4.0 µA/dB.

COMM

gm STAGE

CINT

10mA

MAX

VOUT

BIAS

ISOURCE

400

µA

VPOS

FROM

SETPOINT

SUMMED

DETECTOR

OUTPUTS

Figure 27. Output Interface Circuitry

Thus, for midscale RF input of about 3 mV, which is some 40 dB

above the minimum detector output, this current is 160 µA, and

the output changes by 8 V/µs. When VOUT is connected to VSET,

the rise and fall times are approximately 40 ns (for RL ≥ 10 kΩ ).

The nominal slew rate is 2.5 V/µs. The HF compensation tech-

nique results in stable operation with a large capacitive load, CL,

though the positive-going slew rate is then limited by ISOURCE/CL

to 1 V/µs for CL = 400 pF.

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