3

AT24C21

0405I–SEEPR–7/03

Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is

open-drain driven and may be wire-ORed with any number of other open drain or open

collector devices.

SERIAL CLOCK (VCLK): Upon power-up, the device is in the Transmit-only mode and

will transmit the entire memory contents via the SDA pin with positive signals on the

VCLK pin.

The 1K requires a 7-bit data word address for random word addressing.

Note:

Note:

1. This parameter is characterized and is not 100% tested.

DC Characteristics

(unless otherwise noted).

Symbol

Parameter

Test Condition

Min

Typ

Max

Units

Supply Voltage

2.5

5.5

V

READ at 100 KHz

0.4

1.0

mA

WRITE at 100 KHz

2.0

3.0

mA

Standby Current

3.0

12.0

4.0

30.0

µA

µA

Input Leakage Current

0.10

1.0

µA

I

LO

Output Leakage Current

V

0.05

1.0

µA

V

IL

Input Low Level

(1) SCL, SDA Pin

Input Low Level VCLK Pin

V

-0.6

V

0.8

0.2

× V

CC

V

V

V

V

IH

Input High Level

(1) SCL, SDA Pin

Input High Level VCLK Pin

V

2.0

V

V

V

V

OL

Output Low Level V

I

0.40

V

Pin Capacitance(1)

Applicable over recommended operating range from T

Symbol

Test Condition

Max

Units

Conditions

C

I/O

Input/Output Capacitance (SDA)

8

pF

V

6

pF