CS101 Series

2

(Continued)

• Short-term development using a physical prototyping tool

• One pass design using a physical synthesis tool

• Hierarchical design environment for supporting large-scale circuits

• Support for Signal Integrity, EMI noise reduction

• Support for static timing sign-off

• Optimum package range : FBGA, FC-BGA, PBGA,TEBGA

■ MACRO LIBRARIES (including those in preparation)

1.

Logic cells (about 400 types)

Library sets having three different types of core transistors with a different threshold value are provided.

2.

IP macros

Compliance with the design rules recommended by the industry standard STARC (Semiconductor Technology

Academic Research Center) recommendations which means a wide range of commercially available IP macros

can be used.

Fujitsu plans to offer the following macros.

3.

Special I/O interface macro

• Adder

• AND

• AND-OR

• AND-OR Inverter

• Buffer

• Clock Buffer

• Decoder

• Delay Buffer

• ENOR

• EOR

• Inverter

• Latch

• NAND

• NOR

• OR

• OR-AND

• OR-AND Inverter

• SCAN Flip flop

• Non-SCAN Flip Flop

• Selector

• Others

CPU/DSP

ARM9

DSPs for communications, AV, and similar applications, others

Multi-media processing macro JPEG, MPEG, others

Mixed signal macro

ADC, DAC, OPAMP, others

Compiled macro

RAM (1-port, 2-port), ROM, product sum calculator, others

PLL

Analog PLL

Interface macro

LVDS, SSTL2, HSTL, GTL, others

Fast I/F macro

6 Gbps I/F, 10 Gbps I/F, others