15

3053B–MICRO–3/05

AT89LS51

Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code

data can be read back via the address and data lines for verification. The status of the individ-

ual lock bits can be verified directly by reading them back.

Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-

mal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to

a logic low. The values returned are as follows.

(000H) = 1EH indicates manufactured by Atmel

(100H) = 61H indicates 89LS51

(200H) = 06H

Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the

proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns -

500 ns.

In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase

instruction. In this mode, chip erase is self-timed and takes about 500 ms.

During chip erase, a serial read from any address location will return 00H at the data output.

16. Programming the Flash – Serial Mode

The Code memory array can be programmed using the serial ISP interface while RST is pulled

to V

set high, the Programming Enable instruction needs to be executed first before other operations

can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is

required.

The Chip Erase operation turns the content of every memory location in the Code array into

FFH.

Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected

across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than

1/16 of the crystal frequency. With a 16 MHz oscillator clock, the maximum SCK frequency is 1

MHz.

16.1

Serial Programming Algorithm

To program and verify the AT89LS51 in the serial programming mode, the following sequence is

recommended:

1.

Power-up sequence:

a.

Apply power between VCC and GND pins.

b.

Set RST pin to “H”.

If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 16 MHz clock to

XTAL1 pin and wait for at least 10 milliseconds.

2.

Enable serial programming by sending the Programming Enable serial instruction to pin

MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less

than the CPU clock at XTAL1 divided by 16.

3.

The Code array is programmed one byte at a time in either the Byte or Page mode. The

write cycle is self-timed and typically takes less than 1 ms at 2.7V.

4.

Any memory location can be verified by using the Read instruction that returns the con-

tent at the selected address at serial output MISO/P1.6.