AT89LP214 datasheet(54/90 Pages) ATMEL

54 / 90 page

3538A–MICRO–7/06

AT89LP213/214 [Preliminary]

The CPHA (Clock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate =

baud rate) bits in SPCR control the shape and rate of SCK. The two SPR bits provide four possi-

ble clock rates when the SPI is in master mode. In slave mode, the SPI will operate at the rate of

the incoming SCK as long as it does not exceed the maximum bit rate. There are also four pos-

sible combinations of SCK phase and polarity with respect to the serial data. CPHA and CPOL

determine which format is used for transmission. The SPI data transfer formats are shown in

Figures 18-4 and 18-5. To prevent glitches on SCK from disrupting the interface, CPHA, CPOL,

and SPR should not be modified while the interface is enabled, and the master device should be

enabled before the slave device(s).

Figure 18-4. SPI Transfer Format with CPHA = 0

Note:

*Not defined but normally MSB of character just received.

Figure 18-5. SPI Transfer Format with CPHA = 1

Note:

*Not defined but normally LSB of previously transmitted character.

MSB

LSB

MSB

LSB

SCK CYCLE #

(FOR REFERENCE)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

(FROM MASTER)

MISO

(FROM SLAVE)

SS (TO SLAVE)

AT89LP214 Datasheet(PDF) 54 Page - ATMEL Corporation