TSC80251G2D datasheet(13/77 Pages) ATMEL

13 / 77 page

AT/TSC8x251G2D

4135F–8051–11/06

Special Function

Registers

The Special Function Registers (SFRs) of the TSC80251G2D derivatives fall into the

categories detailed in Table 1 to Table 9.

SFRs are placed in a reserved on-chip memory region S: which is not represented in the

data memory mapping (Figure 5). The relative addresses within S: of these SFRs are

provided together with their reset values in Table . They are upward compatible with the

SFRs of the standard 80C51 and the Intel’s 80C251Sx family. In this table, the C251

core registers are identified by Note 1 and are described in the TSC80251 Program-

mer’s Guide. The other SFRs are described in the TSC80251G1D Design Guide. All the

SFRs are bit-addressable using the C251 instruction set.

Table 1.

C251 Core SFRs

Note:

1. These SFRs can also be accessed by their corresponding registers in the register

file.

Table 2.

I/O Port SFRs

Table 3.

Timers SFRs

Mnemonic

Name

Mnemonic

Name

ACC(1)

Accumulator

SPH(1)

Stack Pointer High - MSB of

SPX

B(1)

B Register

DPL(1)

Data Pointer Low byte - LSB of

DPTR

PSW

Program Status Word

DPH(1)

Data Pointer High byte - MSB

of DPTR

PSW1

Program Status Word 1

DPXL(1)

Data Pointer Extended Low

byte of DPX - Region number

SP(1)

Stack Pointer - LSB of SPX

Mnemonic

Name

Mnemonic

Name

Port 0

Port 2

Port 1

Port 3

Mnemonic

Name

Mnemonic

Name

TL0

Timer/Counter 0 Low

Byte

TMOD

Timer/Counter 0 and 1

Modes

TH0

Timer/Counter 0 High

Byte

T2CON

Timer/Counter 2

Control

TL1

Timer/Counter 1 Low

Byte

T2MOD

Timer/Counter 2 Mode

TH1

Timer/Counter 1 High

Byte

RCAP2L

Timer/Counter 2

Reload/Capture Low

Byte

TL2

Timer/Counter 2 Low

Byte

RCAP2H

Timer/Counter 2

Reload/Capture High

Byte

TH2

Timer/Counter 2 High

Byte

WDTRST

WatchDog Timer Reset

TCON

Timer/Counter 0 and 1

Control

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