8

SY10E136

SY100E136

Micrel, Inc.

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

Figure 4. Programmable Divider Waveforms

Figure 5. 24-bit Programmable Divider Architecture

The exercise of building a programmable divider then

becomes simply determining what value to load into the

counter to accomplish the desired division. Since the load

operation requires a clock pulse, to divide by N, N-1 must

be loaded into the counter. A single E136 device is capable

of divide ratios of 2 to 64, inclusive. Table 1 outlines the

load values for the various divide ratios. Figure 4 presents

the waveforms resulting from a divide by 37 operation. Note

allows the user to choose the polarity of the divide by output.

For single device programmable counters, the E016

counter is probably a better choice than the E136.

The

E016 has an internal feedback to control the reloading of

the counter. This not only simplifies board design, but also

will result in a faster maximum count frequency.

For programmable dividers of larger than 8 bits, the

benefits of the E016 diminishes and, in fact, for very wide

dividers, the E136 will provide the capability of a faster

count frequency. Figure 5 shows the architecture of a 24-

bit programmable divider implemented using E136 counters.

Note the need for one external gate to control the loading of

the entire counter chain. An ideal device for the external

gating of this architecture would be the 4-input OR function

in the 8-lead SOIC ECLinPS Lite™ family. However, the

final decision as to what device to use for external gating

requires a balancing of performance needs, cost and

available board space. Note that because of the need for

external gating, the maximum count frequency of a given

sized programmable divider will be less than that of a single

cascaded counter.

CLOCK

S1

LOAD

100100

100011

000011

000010

000001

000000

LOAD

DIVIDE BY 37

CLK

CLOCK

"LO"

"LO"

LSB

D0 – D5

"LO"

D0 – D5

D0 – D5

MSB

D0 – D5

CLK

CLK

CLK