s 750ps max. LEN to output

s 700ps max. D to output

s Single-ended outputs

s Asynchronous Master Reset

s Dual latch-enables

s Fully compatible with industry standard 10KH,

100K ECL levels

s Internal 75K

s Fully compatible with Motorola MC10E/100E155

s Available in 28-pin PLCC package

FEATURES

The SY10/100E155 offer six 2:1 multiplexers followed

by latches with single-ended outputs, designed for use in

new, high-performance ECL systems. The two external

logical OR operation before use as control for the six

latches are transparent, thus presenting the data from the

both) are at a logic HIGH, the outputs are latched.

The multiplexer operation is controlled by the SEL (Select)

signal which selects one of the two bits of input data at each

mux to be passed through.

The MR (Master Reset) signal operates asynchronously

to take all outputs to a logic LOW.

DESCRIPTION

Rev.: C

Amendment: /1

Issue Date:

February, 1998

6-BIT 2:1

MUX-LATCH

SY10E155

SY100E155

FINAL

BLOCK DIAGRAM

PIN CONFIGURATION

PIN NAMES

Pin

Function

Input Data a

Input Data b

SEL

Data Select Input

Latch Enables

MR

Master Reset

Outputs

SEL

MR

26

27

28

1

2

3

4

18

17

16

15

14

13

12

25 24 23 22 21 20 19

56789

10 11

PLCC

TOP VIEW

J28-1

D

R

Q

MUX

SEL

D

R

Q

MUX

D

R

Q

MUX

D

R

Q

MUX

D

R

Q

MUX

D

R

Q

MUX

MR

SEL

E

N

E

N

E

N

E

N

E

N

E

N

SEL

SEL

SEL

SEL

SEL

1