1997 Sep 08

7

Philips Semiconductors

Preliminary specification

9-fold ESD Transient Suppressor

BZA109TS

DEVICE PLACEMENT AND PRINTED-CIRCUIT BOARD LAYOUT

Circuit board layout is of extreme importance in the suppression of transients. The clamping voltage of the BZA109TS is

determined by the peak transient current and the rate of rise of that current (di/dt). Since parasitic inductances can further

add to the clamping voltage (V = L di/dt) the printed-circuit board layout should use minimal series conductor lengths.

This includes the lead length of the suppression element.

In addition to minimizing conductor length the following printed-circuit board layout guidelines are recommended:

1. Place the suppression element in the area of the input terminals or connectors.

2. Reduce parallel signal paths.

3. Avoid running protection conductors in parallel with unprotected conductors.

4. Minimize all printed-circuit board loop areas including power and ground loops.

5. Minimize the length of the transient return path to ground.

6. Avoid using shared transient return paths to a common ground point.