APW8868B datasheet(21/26 Pages) ANPEC

21 / 26 page

Rev. A.3 - Oct., 2017

www.anpec.com.tw

APW8868B

Application Information (cont.)

- Keep the switching nodes (UGATE, LGATE, BOOT, and

PHASE) away from sensitive small signal nodes(VFB,

VTTREF, and CS) since these nodes are fast moving

signals. Therefore, keep traces to these nodes as short

as possible and there should be no other weak signal

traces in parallel with theses traces on any layer.

- The signals going through theses traces have both high

dv/dt and high di/dt, with high peak charging and dis-

charging current. The traces from the gate drivers to the

MOSFETs (UGATE and LGATE) should be short and wide.

- Place the source of the high-side MOSFET and the drain

of the low-side MOSFET as close as possible. Minimiz-

ing the impedance with wide layout plane between the

two pads reduces the voltage bounce of the node.

- Decoupling capacitor, the resistor dividers, boot

capacitors, and current limit stetting resistor should be

close their pins. (For example, place the decoupling ce-

ramic capacitor near the drain of the high-side MOSFET

as close as possible. The bulk capacitors are also placed

near the drain).

- The input capacitor should be near the drain of the up-

per MOSFET; the high quality ceramic decoupling capaci-

tor can be put close to the VCC and GND pins; the VTTREF

decoupling capacitor should be close to the VTTREF pin

and GND; the VDDQ and VTT output capacitors should

be located right across their output pin as close as pos-

sible to the part to minimize parasitic. The input capacitor

GND should be close to the output capacitor GND and

the lower MOSFET GND.

- The drain of the MOSFETs (VIN and PHASE nodes)

should be a large plane for heat sinking. And PHASE pin

traces are also the return path for UGATE. Connect this

pin to the converter

’s upper MOSFET source.

- The APW8868B used ripple mode control. Build the re-

sistor divider close to the VFB pin so that the high imped-

ance trace is shorter. And the VFB pin traces can

’t be

closed to the switching signal traces (UGATE, LGATE,

BOOT, and PHASE).

- The PGND trace should be a separate trace, and inde-

pendently go to the source of the low-side MOSFETs for

current limit accuracy.

Layout Consideration

Figure3. Recommended Minimum Footprint

0.4mm

0.2mm

0.5mm

3mm

* Just Recommend

TQFN3x3-20

0.5mm *

3mm

1.66 mm

0.17mm

APW8868B Datasheet(PDF) 21 Page - Anpec Electronics Coropration

APW8868B Datasheet(HTML) 21 Page - Anpec Electronics Coropration

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL