Philips Semiconductors

Product specification

GTL2010

10-bit GTL Processor Voltage Clamp

2

1999 Apr 05

853-2153 21178

FEATURES

DESCRIPTION

The GTL2010 is a high speed 10-bit voltage clamp. The low

ON-state resistance of the clamp allows connections to be made

with minimal propagation delay.

The device is organized as one 10-bit voltage clamp. When S or D

is low, the clamp is in the ON–state and a low resistance connection

exists between the S and D ports. When S port and D port are high,

the clamp is in the OFF-state and a very high impedance exists

between the S and D ports. When port D is high, the voltage on the

S port is clamped to the applied reference voltage on the GREF

port.

PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

GND

SA00527

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

Propagation delay

Sn to Dn

1.5

ns

Channel capacitance (OFF-state)

7.5

pF

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

24-Pin Plastic TSSOP Type II

0

°C to +85°C

GTL2010 PW

GTL2010PW DH

SOT355–1

PIN DESCRIPTION

PIN NUMBER

SYMBOL

NAME AND FUNCTION

1

GND

Ground (0V)

2

Source of reference

transistor

3 – 12

13 – 22

23

Drain of reference

transistor

24

Gate of reference

transistor

FUNCTION TABLE

L

L

H

H

H = High voltage level

L

= Low voltage level

Z = High impedance “off ” state

CLAMP SCHEMATIC

SA00526