CDP1802BCEX datasheet(18/28 Pages) INTERSIL

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INTERRUPT, DMA-lN, DMA-OUT (3 I/O Requests)

These inputs are sampled by the CPU during the interval

between the leading edge of TPB and the leading edge of

TPA.

Interrupt Action - X and P are stored in T after executing

current instruction; designator X is set to 2; designator P is

set to 1; interrupt enable is reset to 0 (inhibit); and instruction

execution is resumed. The interrupt action requires one

machine cycle (S3).

DMA Action - Finish executing current instruction; R(0)

points to memory area for data transfer; data is loaded into

or read out of memory; and increment R(0).

NOTE: In the event of concurrent DMA and Interrupt requests,

DMA-lN has priority followed by DMA-OUT and then Interrupt.

SC0, SC1, (2 State Code Lines)

These outputs indicate that the CPU is: 1) fetching an

instruction, or 2) executing an instruction, or 3) processing a

DMA request, or 4) acknowledging an interrupt request. The

levels of state code are tabulated below. All states are valid

at TPA. H = VCC, L = VSS.

TPA, TPB (2 Timing Pulses)

Positive pulses that occur once in each machine cycle (TPB

follows TPA). They are used by I/O controllers to interpret

codes and to time interaction with the data bus. The trailing

edge of TPA is used by the memory system to latch the

higher-order byte of the 16-bit memory address. TPA is sup-

pressed in IDLE when the CPU is in the load mode.

MA0 to MA7 (8 Memory Address Lines)

In each cycle, the higher-order byte of a 16-bit CPU memory

address appears on the memory address lines MA0-7 first.

Those bits required by the memory system can be strobed

into external address latches by timing pulse TPA. The low

order byte of the 16-bit address appears on the address lines

after the termination of TPA. Latching of all 8 higher-order

address bits would permit a memory system of 64K bytes.

MWR (Write Pulse)

A negative pulse appearing in a memory-write cycle, after

the address lines have stabilized.

MRD (Read Level)

A low level on MRD indicates a memory read cycle. It can be

used to control three-state outputs from the addressed mem-

ory which may have a common data input and output bus. If a

memory does not have a three-state high-impedance output,

MRD is useful for driving memory/bus separator gates. It is

also used to indicate the direction of data transfer during an

I/O instruction. For additional information see Table 1.

Single bit output from the CPU which can be set or reset

under program control. During SEQ or REQ instruction exe-

cution, Q is set or reset between the trailing edge of TPA and

the leading edge of TPB.

CLOCK

Input for externally generated single-phase clock. The clock is

counted down internally to 8 clock pulses per machine cycle.

XTAL

Connection to be used with clock input terminal, for an exter-

nal crystal, if the on-chip oscillator is utilized. The crystal is

connected between terminals 1 and 39 (CLOCK and XTAL)

in parallel with a resistance (10M

Ω typ). Frequency trimming

capacitors may be required at terminals 1 and 39. For addi-

tional information, see Application Note AN6565.

WAIT, CLEAR (2 Control Lines)

Provide four control modes as listed in the following truth table:

VDD, VSS, VCC (Power Levels)

The internal voltage supply VDD is isolated from the

Input/Output voltage supply VCC so that the processor may

operate at maximum speed while interfacing with peripheral

devices operating at lower voltage. VCC must be less than or

equal to VDD. All outputs swing from VSS to VCC. The recom-

mended input voltage swing is VSS to VCC.

Architecture

The CPU block diagram is shown in Figure 2. The principal

feature of this system is a register array (R) consisting of six-

teen 16-bit scratchpad registers. Individual registers in the

array (R) are designated (selected) by a 4-bit binary code

from one of the 4-bit registers labeled N, P and X. The con-

tents of any register can be directed to any one of the follow-

ing three paths:

1. The external memory (multiplexed, higher-order byte first,

on to 8 memory address lines).

2. The D register (either of the two bytes can be gated to D).

3. The increment/decrement circuit where it is increased or

decreased by one and stored back in the selected 16-bit

STATE TYPE

STATE CODE LINES

SC1

SC0

S0 (Fetch)

S1 (Execute)

S2 (DMA)

S3 (Interrupt)

CLEAR

WAIT

MODE

LOAD

RESET

PAUSE

RUN

CDP1802A, CDP1802AC, CDP1802BC

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