January 1995

4

Philips Semiconductors

Product specification

Programmable divide-by-n counter

HEF4059B

LSI

Figure 3 illustrates the operation of the counter in mode

÷ 8 starting from the preset state 3.

Fig.3 Total count of 3.

CP INPUT

internal state

of counter

O OUTPUT

If the ‘master preset’ mode is started two clock cycles or

less before an output pulse, the output pulse will appear at

the time due. If the ‘master preset’ mode is not used the

counter is preset in accordance with the ‘jam inputs when

the output pulse appears. A HIGH level at the latch enable

input (EL) will cause the counter output to go HIGH once

an output pulse occurs, and remain in the HIGH state until

EL input returns to LOW. If the EL input is LOW, the output

pulse will remain HIGH for only one cycle of the clock input

signal.

operates in the ‘preset inhibit’ mode, with which the

dividend of the counter is fixed to 10 000, independent of

the state of the jam inputs.

When in the same state of mode select inputs EL = H, the

counter operates in the normal

÷ 10 mode, however,

without the latch operation at the output.

Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.