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5-Bit Nonvolatile Register

Interface

Logic

Address:

1001110

1-Bit

Transparent

Latch

4-Bit 1-of-2 Multiplexer

NON-MUXED

OUT

MUX OUT A

MUX OUT B

MUX OUT C

MUX OUT D

MUX IN A

SCL

SDA

OVERRIDE

WP

MUX IN B

MUX IN C

MUX IN D

MUX SELECT

1

2

15

3

4

5

6

7

13

14

12

11

10

9

PCA8550

NONVOLATILE 5-BIT REGISTER

SCPS050C – MARCH 1999 – REVISED MAY 2005

FUNCTION TABLE

INPUTS

OUTPUTS

MUX SELECT

OVERRIDE

MUX OUT

NON-MUXED OUT

L

L

L

L

L

H

Nonvolatile register

Nonvolatile register

H

X

MUX IN

(1)

The latched NON-MUXED OUT state is the value present on the NON-MUXED OUT output at the

time the MUX SELECT input transitions from the low to the high state.

LOGIC DIAGRAM (POSITIVE LOGIC)

2