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1

2

3

4

5

6

7

8

9

S

0

1

0

0

A2

A1

A0

1

A

7

6

5

4

3

2

1

0

A

I0.x

7

6

5

4

3

2

1

0

A

I1.x

7

6

5

4

3

2

1

0

A

I0.x

7

6

5

4

3

2

1

0

1

I1.x

P

R/W

SCL

SDA

INT

Read From Port 0

Data Into Port 0

Read From Port 1

Data Into Port 1

Acknowledge

From Master

Acknowledge

From Slave

Acknowledge

From Master

Acknowledge

From Master

No Acknowledge

From Master

1

2

3

4

5

6

7

8

9

S

0

1

0

0

A2 A1 A0

1

A

A

A

A

1

P

R/W

SCL

SDA

INT

00

10

03

12

11

12

Read From Port 0

Data Into Port 0

Read From Port 1

Data Into Port 1

Data 02

Data 01

Data 00

Data 03

Data

Data

Data 10

Acknowledge

From Slave

Acknowledge

From Master

Acknowledge

From Master

Acknowledge

From Master

No Acknowledge

From Master

I0.x

I1.x

I0.x

I1.x

PCA9535

WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

SCPS129E – AUGUST 2005 – REVISED FEBRUARY 2007

A.

Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest

acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read

Input Port register).

B.

This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from P port (see Figure 8 for these details).

Figure 9. Read Input Port Register, Scenario 1

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A.

Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest

acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read

Input Port register).

B.

This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from P port (see Figure 8 for these details).

Figure 10. Read Input Port Register, Scenario 2

12

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