9

FIGURE 16. ENOB vs INPUT FREQUENCY

5.00

4.50

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

3.00

6.00

5.70

5.40

5.10

4.80

4.50

4.20

3.90

3.60

3.30

Pin Descriptions

PIN NUMBER

NAME

DESCRIPTION

DIP

SOIC

1

1

B6

Bit 6, Output (MSB).

2

2

OF

Overflow, Output.

33, 4

Digital Ground.

4

5

VZ

Zener Reference Output.

5

6

CE2

Three-State Output Enable Input, Active Low. See Table 1.

67

CE1

Three-State Output Enable Input, Active High. See Table 1.

7

8

CLK

Clock Input.

8

9

Phase

Sample clock phase control input. When PHASE is low, “Sample Unknown” occurs

when the clock is low and “Auto Balance” occurs when the clock is high (see text).

910

Reference Voltage Positive Input.

10

11

Reference Voltage Negative Input.

11

12

Analog Signal Input.

12

13, 14

Power Supply, +5V.

13

15

B1

Bit 1, Output (LSB).

14

16

B2

Bit 2, Output.

15

17

B3

Bit 3, Output.

16

18

REF(CTR)

Reference Ladder Midpoint.

17

19

B4

Bit 4, Output.

18

20

B5

Bit 5, Output.

CA3306, CA3306A, CA3306C