January 1995

8

Philips Semiconductors

Product specification

Universal timer module

HEF4753B

LSI

7. Digital pulse duration selector mode (Y = Z = LOW)

This mode is a combination of two circuits, both used for frequency recognition. Both circuits are driven by the same clock

and same input signal, but programmed for different frequencies. The LFC input of the low-frequency circuit is set to logic

LOW, the output is connected to the LFC input of the high-frequency circuit, whose output (OUT) is the ‘filter’ output. The

delay time depends on the same facts as given in note 2.. For timing diagram see Fig.9.

Notes to operating modes

1. The number of clocks for one cycle in the counter and divider mode is:

a. Contents of programmable counter plus one if X = W = LOW.

b. Contents of programmable counter multiplied by 16, 256 or 4096 if X and/or W = HIGH.

2. The delay in the modes 3, 4, 6 and 7, and the delay which is identical to the maximum duration of the transient pulse

in mode 5 depend on the optional divided clock frequency, the input conditions of the 8-bit presetable counter and in

addition, different times of propagation delays, jitter and maximum one half of a clock frequency period.

Fig.9

Minimum dividing number is 3.

A

B

C

D

E

F

G

H

W

X

LFC

Y

Z

L

L

L

HHHHH

L

L

L

H

H

IC1

L

L

HHHHHH

L

L

OUT

(IC1)

L

L

IC2