30

Am29F002B/Am29F002NB

21527D5 November 1, 2006

D A TA

SH EE T

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

High Z

DQ7

DQ0–DQ6

Complement

True

Addresses

VA

VA

VA

Status Data

Complement

Status Data

True

Valid Data

Valid Data

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 13.

Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

DQ6/DQ2

Addresses

VA

VA

VA

Valid Data

Valid Status

Valid Status

(first read)

(second read)

(stops toggling)

Valid Status

VA

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 14.

Toggle Bit Timings (During Embedded Algorithms)