AM29LV160M datasheet(35/63 Pages) AMD

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January 31, 2007 25974B5

Am29LV160M

Data

Sheet

Write Operation Status

The device provides several bits to determine the status of a write operation:

DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 12, on page 38 and the following

subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each

offer a method for determining whether a program or erase operation is complete

or in progress. These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded

Algorithm is in progress or completed, or whether the device is in Erase Suspend.

Data# Polling is valid after the rising edge of the final WE# pulse in the program

or erase command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the com-

plement of the datum programmed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to DQ7. The system must

provide the program address to read valid status information on DQ7. If a pro-

gram address falls within a protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading array data.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.

When the Embedded Erase algorithm is complete, or if the device enters the

Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to

the complement/true datum output described for the Embedded Program algo-

rithm: the erase function changes all the bits in a sector to “1”; prior to this, the

device outputs the “complement,” or “0.” The system must provide an address

within any of the sectors selected for erasure to read valid status information on

DQ7.

After an erase command sequence is written, if all sectors selected for erasing

are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the

device returns to reading array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

When the system detects DQ7 changes from the complement to true data, it can

read valid data at DQ7–DQ0 on the following read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as-

serted low. Figure 19 , on pag e 48 , Da ta# Polling Timings

(During Embedded Algorithms), illustrates this.

Table 12, on page 38 shows the outputs for Data# Polling on DQ7. Figure 7, on

page 34 shows the Data# Polling algorithm.

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