AM29LV033MU datasheet(12/61 Pages) SPANSION

12 / 61 page

Am29LV033MU

September 12, 2006

DA TA

SH EET

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1.

Device Bus Operations

Legend: L = Logic Low = V

IL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,

IN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A21:A0. Sector addresses are A21:A16.

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

3. D

IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

VersatileIO

™ (V

IO) Control

The VersatileIO™ (VIO) control allows the host system

to set the voltage levels that the device generates and

tolerates on CE# and DQ I/Os to the same voltage

level that is asserted on VIO. See Ordering Information

for VIO options on this device.

For example, a VI/O of 1.65–3.6 volts allows for I/O at

the 1.8 or 3 volt levels, driving and receiving signals to

and from other 1.8 or 3 V devices on the same data

bus.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V

IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V

IH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read-Only Operations table for timing speci-

fications and to Figure 13 for the timing diagram. Refer

Operation

CE#

OE#

WE#

RESET#

ACC

Addresses

(Note 2)

DQ7–

DQ0

Read

OUT

Write (Program/Erase)

(Note 3)

Accelerated Program

(Note 3)

Standby

CC ±

0.3 V

CC ±

0.3 V

High-Z

Output Disable

High-Z

Reset

High-Z

Sector Group Protect (Note 2)

SA, A6=L, A3=L,

A2=L, A1=H, A0=L

(Note 3)

Sector Group Unprotect

(Note 2)

SA, A6=H, A3=L,

A2=L, A1=H, A0=L

(Note 3)

Temporary Sector Group

Unprotect

(Note 3)

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