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AM49PDL129AH Datasheet(PDF) 13 Page - SPANSION

Part # AM49PDL129AH
Description  128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
PDF  82 Pages
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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AM49PDL129AH Datasheet(HTML) 13 Page - SPANSION

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December 18, 2003
Am49PDL127AH/Am49PDL129AH
11
ADV ANCE
I N FO RMAT I O N
PIN DESCRIPTION
A19–A0
= 20 Address Inputs (Common)
A21-A20
= 2 Address Inputs (Flash)
A22
= Address Input (PDL127 only)
(Flash)
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
CE#f1
= Chip Enable 1 (Flash) (PDL 127
only)
CE#f1, CE#f2 = Chip Enable Inputs. CE#f1 controls
the 64 Mb in Banks 1A and 1B.
CE#f2 controls the 64 Mb in Banks
2A and 2B.
CE#1ps
= Chip Enable 1 (pSRAM) (PDL129
only)
CE2ps
= Chip Enable 2 (pSRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output and open drain.
When RY/BY# = VIH, the device is
ready to accept read operations and
commands. When RY/BY# = VOL,
the device is either executing an em-
bedded algorithm or the device is
executing a hardware reset opera-
tion.
UB#s
= Upper Byte Control (pSRAM)
LB#s
= Lower Byte Control (pSRAM)
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Write Protect/Acceleration Input.
When WP/ACC#= VIL, the highest
and lowest two 4K-word sectors are
write protected regardless of other
sector protection configurations.
When WP/ACC#= VIH, these sector
are unprotected unless the DYB or
PPB is programmed. When WP/
ACC#= 12V, program and erase op-
erations are accelerated.
VCCf
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
VCCs
= pSRAM Power Supply
VSS
= Device Ground (Common)
NC
= Pin Not Connected Internally
LOGIC SYMBOL
20
16
DQ15–DQ0
A19–A0
CE#f1
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
A21-A20
LB#s
CE#1ps
CE2ps
CE#f2 (PDL129 Only)
A22 (PDL127 Only)



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