USB3300 datasheet(40/49 Pages) SMSC

40 / 49 page

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface

Datasheet

Revision 1.06 (07-19-06)

SMSC USB3300

DATASHEET

Note:

This is the same as Table 40, Section 4.4 of the ULPI 1.1 specification.

6.2.3

Bias Generator

This block consists of an internal bandgap reference circuit used for generating the driver current and

the biasing of the analog circuits. This block requires an external 12K

Ω, 1% tolerance, external

reference resistor connected from RBIAS to ground.

6.3

Crystal Oscillator and PLL

The USB3300 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference

clock that is used by the PHY during both transmit and receive. The USB3300 requires a clean 24MHz

crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY

may not operate correctly.

The USB3300 can use either a crystal or an external clock oscillator for the 24MHz reference. The

crystal is connected to the XI and XO pins as shown in the application diagram, Figure 7.1. If a clock

oscillator is used the clock should be connected to the XI input and the XO pin left floating. When a

external clock is used the XI pin is designed to be driven with a 0 to 3.3 volt signal. When using an

external clock the user needs to take care to ensure the external clock source is clean enough to not

corrupt the high speed eye performance.

Once the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz

clock. The USB3300 is guaranteed to start the clock within the time specified in Table 5.2. The

USB3300 does not support using an external 60MHz clock input.

For Host Applications the USB3300 implements the ULPI AutoResume bit in the Interface Control

more details please see sections 7.1.77 and 7.9 of the USB specification.

6.4

Internal Regulators and POR

The USB3300 includes an integrated set of built in power management functions, including a POR

generator. Internal regulators enable the USB3300 to be powered from a single 3.3 volt power supply,

thereby reducing the bill of materials and simplifying product design.

OTG device, Peripheral Chirp

00b

10b

OTG device, Peripheral HS

00b

OTG device, Peripheral FS

01b

00b

OTG device, Peripheral HS/FS Suspend

01b

00b

OTG device, Peripheral HS/FS Resume

01b

10b

OTG device, Peripheral Test J/Test K

00b

10b

Table 6.8 DP/DM termination vs. Signaling Mode (continued)

SIGNALING MODE

RESISTOR SETTINGS

USB3300 Datasheet(PDF) 40 Page - SMSC Corporation

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