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AM50DL128CH85IS Datasheet(PDF) 62 Page - SPANSION |
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AM50DL128CH85IS Datasheet(HTML) 62 Page - SPANSION |
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62 / 66 page ![]() 60 Am50DL128CH February 6, 2004 ADV ANCE I N FO RMAT I O N pSRAM ADDRESS SKEW Figure 34. Read Address Skew Note: If multiple invalid address cycles shorter than t RC min occur for a period greater than 10 µs, at least one valid address cycle over t RC min is required during that period. Figure 35. Write Address Skew Note: If multiple invalid address cycles shorter than t WC min occur for a period greater than 10 µs, at least one valid address cycle over t WC min, in addition to tWP min, is required during that period. CE#1 WE# Address tRC min over 10 µs CE#1 WE# Address tWP min tWC min over 10 µs |
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