ISL51002 datasheet(15/32 Pages) INTERSIL

15 / 32 page

December 22, 2006

0x27

ABLC Configuration, (0x40)

ABLC Disable

0: ABLC on (default) - use 10-bit digital offset control.

0x000 = -0x200 LSB offset, 0x3FF = +0x1FF LSB offset,

0x200 = 0x000 LSB offset

1: ABLC off - use 10-bit offset DACs, bypass digital adder

(add/subtract nothing, but keep same delay through

channel)

Offset DAC Range

0: ±1/2 ADC fullscale (1 LSB = 1 ADC LSBs)

1: ±1/4 ADC fullscale (1 LSB = 0.5 ADC LSBs)

3:2

ABLC Pixel Width

Number of black pixels averaged every line for ABLC function

00: 16 pixels [default]

01: 32 pixels

10: 64 pixels

11: 128 pixels

6:4

ABLC Bandwidth

ABLC Time constant (lines) = 2([5+6:4])

000 = 32 lines

100 = 512 lines (default)

111 = 4096 lines

0x28

Output Format 1, (0x00)

Data Output Format

0: 4:4:4 (24/30-bit output)

1: 4:2:2 (16/20-bit output on G and R)

4:2:2 Order

0: First pixel on R channel is U

1: First pixel on R channel is V

4:2:2 Processing

0: U, V fitered (high quality)

1: Odd U, V pixels dropped (lower quality)

8-bit Mode

0: All 10 bits of each channel active

1: 2 LSBs of each channel driven low (in 8-bit applications,

keep the LSBs from switching and generating noise)

5:4

Oversampling

00: Normal operation (1x sampling)

01:2x oversampling, 2 samples averaged at ADC output

10:4x oversampling, 4 samples averaged at ADC output

11:8x oversampling, 8 samples averaged at ADC output

In Oversampling mode, the HTOTAL, DC Restore/ABLC Start,

DC Restore Width, and ABLC width values are automatically

multiplied by the oversampling ratio. The pixel clock is divided

by the oversampling ratio when the data is decimated.

Decimator is reset on trailing edge of HSYNC.

RGB2YUV Color Space

Conversion Enable

0: CSC Disabled

1: CSC Enabled

Note: The data delay through the entire AFE is identical with

CSC on and CSC off.

ADDRESS

(DEFAULT VALUE)

BITS

FUNCTION NAME

DESCRIPTION

ISL51002

ISL51002 Datasheet(PDF) 15 Page - Intersil Corporation

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