P83CL782 datasheet(21/76 Pages) PHILIPS

21 / 76 page

1997 Mar 14

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontrollers with

UART and I2C-bus

P83CL781; P83CL782

12 REDUCED POWER MODES

There are two software-selectable modes which further

reduce power consumption: ‘Idle’ and ‘Power-down’.

12.1

Idle mode

Operation in Idle mode permits the interrupt, serial ports

and timer blocks to continue to function while the clock to

the CPU is halted.

Idle mode is entered by setting the IDL bit in the Power

Control Register (PCON.0, see Table 5). The instruction

that sets IDL is the last instruction executed in the normal

operating mode before the Idle mode is activated.

Once in the Idle mode, the CPU status is preserved along

with the Stack Pointer, Program Counter, Program Status

Word and Accumulator. The RAM and all other registers

maintain their data during Idle mode. The status of the

external pins during Idle mode is shown in Table 4.

The following functions remain active during the Idle

mode:

• Timer 0, Timer 1 and Timer 2

• UART, I2C-bus interface

• External interrupt.

These functions may generate an interrupt or reset; thus

ending the Idle mode.

There are two ways to terminate the Idle mode:

1. Activation of any enabled interrupt will cause PCON.0

to be cleared by hardware thus terminating the Idle

mode. The interrupt is serviced, and following the

RETI instruction, the next instruction to be executed

will be the one following the instruction that put the

device in the Idle mode. The flag bits GF0 and GF1

may be used to determine whether the interrupt was

received during normal execution or during the Idle

mode. For example, the instruction that writes to

PCON.0 can also set or clear one or both flag bits.

When the Idle mode is terminated by an interrupt, the

service routine can examine the status of the flag bits.

2. The second way of terminating the Idle mode is with an

external hardware reset, or an internal reset caused by

an overflow of Timer T2. Since the oscillator is still

running, the hardware reset is required to be active for

two machine cycles (24 oscillator periods) to complete

the reset operation. Reset redefines all SFRs but does

not affect the on-chip RAM.

12.2

Power-down mode

Operation in Power-down mode freezes the oscillator.

The internal connections which link both Idle and

Power-down signals to the clock generation circuit are

shown in Fig.12.

Power-down mode is entered by setting the PD bit in the

Power Control Register (PCON.1, see Table 5).

The instruction that sets PD is the last executed prior to

going into the Power-down mode.

Once in the Power-down mode, the oscillator is stopped.

The contents of the on-chip RAM and the SFRs are

preserved. The port pins output the value held by their

respective SFRs. ALE and PSEN are held LOW.

In the Power-down mode, VDD may be reduced to

minimize circuit power consumption. The supply voltage

must not be reduced until the Power-down mode is

entered, and must be restored before the hardware reset

is applied which will free the oscillator. Reset should not be

released until the oscillator has restarted and stabilized.

12.3

Wake-up from Power-down mode

When in Power-down mode the controller can be

woken-up with either the external interrupts INT2 to INT9,

or a reset operation. The wake-up operation has two basic

approaches as explained in Section 12.3.1; 12.3.2 and

illustrated in Fig.13.

12.3.1

WAKE-UP USING INT2 TO INT9

If any of the interrupts INT2 to INT9 are enabled, the

device can be woken-up from the Power-down mode with

the external interrupts. To ensure that the oscillator is

stable before the controller restarts, the internal clock will

remain inactive for 1536 oscillator periods. This is

controlled by an on-chip delay counter.

12.3.2

WAKE-UP USING RST

To wake-up the P83CL78x, the RST pin must be kept

HIGH for a minimum of 24 periods. The on-chip delay

counter is inactive. The user must ensure that the oscillator

is stable before any operation is attempted.

P83CL782 Datasheet(PDF) 21 Page - NXP Semiconductors

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