X5083PIZ datasheet(17/21 Pages) INTERSIL

Part #	X5083PIZ

Description	CPU Supervisor with 8Kbit SPI EEPROM

PDF	21 Pages

Scroll/Zoom	100%

Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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17 / 21 page

FN8127.3

June 15, 2006

CS vs. RESET Timing

RESET Output Timing

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

VTRIP

Reset trip point voltage, X5083PT-4.5A (Note 6)

Reset trip point voltage, X5083PT

Reset trip point voltage, X5083PT-2.7A

Reset trip point voltage, X5083PT-2.7

4.5

4.25

2.85

2.55

4.63

4.38

2.93

2.63

4.75

4.5

3.00

2.7

tPURST

Power-up reset time out

100

200

280

tRPD (Note 5)

VCC detect to reset/output

500

tF (Note 5)

VCC fall time

0.1

tR (Note 5)

VCC rise time

0.1

VRVALID

Reset valid VCC

NOTES:

5. This parameter is periodically sampled and not 100% tested.

6. PT = Package/Temperature

tCST

RESET

tWDO

tRST

tWDO

tRST

RESET Output Timing

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

tWDO

Watchdog time out period,

WD1 = 1, WD0 = 1(default)

WD1 = 1, WD0 = 0

WD1 = 0, WD0 = 1

WD1 = 0, WD0 = 0

100

450

OFF

200

600

1.4

300

800

sec

tCST

CS pulse width to reset the watchdog

400

tRST

Reset time out

100

200

300

X5083

X5083PIZ Datasheet(PDF) 17 Page - Intersil Corporation

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